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[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] dds_rom

Description: 此为Verilog编写DDS时，常用模块，为rom模块。-This is the Verilog write DDS, the common module, the module for the rom.
Platform: | Size: 5120 | Author: name | Hits:

[VHDL-FPGA-Verilog] FPGA_exp

Description: 一个开发板培训项目的所有Verilog程序例子 其中包括 led 分频 M4kram Rom 等程序-Verilog examples
Platform: | Size: 12810240 | Author: 张明 | Hits:

[VHDL-FPGA-Verilog] rom_uart

Description: 使用verilog HDL编写的rom读取 后串口发送程序 使用的 altera celone器件-Rom prepared using verilog HDL reading program after the serial port device for use altera celone
Platform: | Size: 625664 | Author: 张明 | Hits:

[VHDL-FPGA-Verilog] LIP2242CORE_otp_rom

Description: Verilog OTP ROM source code
Platform: | Size: 297984 | Author: jc | Hits:

[VHDL-FPGA-Verilog] SOU

Description: 这是用C写的正弦函数定点数据生成代码，内容是生成verilog中RAM或者ROM和Matlab处理时的所用的数据。-It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
Platform: | Size: 1024 | Author: wolly | Hits:

[VHDL-FPGA-Verilog] romPlcd1602

Description: 用verilog hdl实现从fpga内部rom中读取数据在lcd1602上显示-The data in the fpga rom is read out and shown in lcd1602 by verilog hdl
Platform: | Size: 3072 | Author: sxy | Hits:

[VHDL-FPGA-Verilog] mem_test

Description: ROM存储器的Verilog测试程序，希望对大家有帮助！-ROM memory of the Verilog test program, we want to help!
Platform: | Size: 409600 | Author: sun pei | Hits:

[VHDL-FPGA-Verilog] ROM_controller

Description: rom controller source code verilog
Platform: | Size: 1024 | Author: seoul | Hits:

[VHDL-FPGA-Verilog] writing

Description: 关于RAM/ROM的一个写操作的程序，语言为verilog-On RAM/ROM, a write operation procedures, language verilog
Platform: | Size: 1024 | Author: 刘春 | Hits:

[VHDL-FPGA-Verilog] VGA_ROMCHAR

Description: verilog源代码，实现将字符数据存储到rom里面，在输出到vga显示，适用vertex5-verilog source code to achieve the character data stored in the rom inside, in the output to vga display for vertex5
Platform: | Size: 1897472 | Author: flier | Hits:

[VHDL-FPGA-Verilog] rom_verilog

Description: verilog 源代码，非常简单的一种ROM的可综合的写法，适合新手学习之用。-verilog source code，simply implementation of ROM with synthesisable coding-sytle， special for the beginners.
Platform: | Size: 1024 | Author: 李海华 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: ROM 控制，verilog 语言描述的，可直接编译，希望对大家有用-ROM control
Platform: | Size: 7168 | Author: 舒旭 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 基于FPGA的rom程序（verilog）-rom procedure
Platform: | Size: 2048 | Author: 杨涛 | Hits:

[VHDL-FPGA-Verilog] DDS-frequency-synthesizer

Description: 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Starting from the design requirements, this paper presents the detailed design of the DDS process, including the various modules of the design ideas, schematics, Verilog language code. The general idea of frequency control word and phase control word to control the address of the ROM memory table of the sine function and the corresponding get its amplitude value, and ultimately achieve the purpose of waveform output needs.
Platform: | Size: 814080 | Author: 任健铭 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Platform: | Size: 3147776 | Author: vice | Hits:

[Other] GenRomSch

Description: Rom的二进制文件转换成verilog 文件-Rom bin file changed to verilog file
Platform: | Size: 1024 | Author: zhengzh37 | Hits:

[VHDL-FPGA-Verilog] music_player

Description: 用Verilog语言在FPGA上实现了音乐播放这一功能。预先将音乐《北京欢迎你》转换保存到FPGA的ROM中，由设计的音乐播放器按时序读出数据，予以播放。-Using Verilog language in FPGA realize the function of playing music.The music of "welcome to Beijing" was transformed and saved in FPGA ROM, the data was read by music player in the time sequence and played .
Platform: | Size: 730112 | Author: 姜伟 | Hits:

[VHDL-FPGA-Verilog] cdromsrc

Description: Verilog HDL应用程序设计实例精讲的书籍光盘代码-Books CD-ROM code Verilog HDL application design example 精讲
Platform: | Size: 125952 | Author: xiao | Hits:

[Other] Pro_19

Description: Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
Platform: | Size: 630784 | Author: 夏九星 | Hits:
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